Metal high dielectric constant (high-k) transistors, or “MHK transistors”, are experiencing extremely active development in the industry. One observed problem with such transistors relates to the presence of an elevated outer fringe capacitance Cof, on the order of 40-80 aF/μm. This elevated capacitance Cof occurs because the gate sidewall of an MHK transistor no longer depletes as in a transistor with a conventional polysilicon gate. The elevated value of outer fringe capacitance Cof is of concern because it at least impairs high frequency operation of the MHK transistor. The elevated value of this capacitance Cof has a performance impact of approximately 1.25% per 10 aF, resulting in a 5%-10% decrease in performance.
Also, with the lack of gate length scaling in recent technologies, alternatives to improve short channel effects so that the gate length may be reduced become critical to reduce the overall device dimensions enough to permit scaling. However, current technologies do not provide a reduction in the parasitic Miller capacitance when metal-like materials (such as TiN) are used.